low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs ics8316 idt ? / ics ? 1-to-16, 1.2v lvcmos fanout buffer 1 ics8316ak rev. b february 29, 2008 g eneral d escription the ics8316 is a low skew, 1-to-16 lvcmos/lvttl fanout buffer with 1.2v lvcmos outputs and a member of the hiperclocks? family of high perfor- mance clock solutions from idt. the ics8316 single ended clock input accepts lvcmos or lvttl input levels. the low impedance lvcmos outputs are designed to drive 50 series or parallel terminated transmission lines. guaranteed output and part-to-part skew characteristics along with the 1.2v output makes the ics8316 ideal for high per- formance, single ended applications that also require a limited output voltage. b lock d iagram p in a ssignment f eatures ? sixteen 1.2v lvcmos / lvttl outputs ? lvcmos / lvttl clock input ? maximum output frequency: 150mhz ? output skew: 380ps (maximum) ? propagation delay: 4.6ns (maximum) ? 3.3v core/1.2v output operating supply mode ? 0c to 70c ambient operating temperature ? industrial temperature information available upon request ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v ddo qc0 qc1 qc2 qc3 gnd oec gnd v ddo qa0 qa1 qa2 qa3 gnd oea clk ics8316 32-lead vfqfn 5mm x 5mm x 0.925 package body k package top view qa0:qa3 clk oea oeb oec oed v dd oeb gnd qb3 qb2 qb1 qb0 v ddo gnd oed gnd qd3 qd2 qd1 qd0 v ddo 4 4 4 4 qb0:qb3 qc0:qc3 qd0:qd3
idt ? / ics ? 1-to-16, 1.2v lvcmos fanout buffer 2 ics8316ak rev. b february 29, 2008 ics8316 low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs t able 1. p in d escriptions t able 2. p in c haracteristics t able 3a. o utput e nable and c lock e nable f unction t able t able 3b. c lock i nput f unction t able r e b m u ne m a ne p y tn o i t p i r c s e d 5 2 , 4 2 , 6 1 , 1v o d d r e w o p. s n i p y l p p u s t u p t u o 5 , 4 , 3 , 23 a q , 2 a q , 1 a q , 0 a qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o k c o l c a k n a b , 7 1 , 1 1 , 6 2 3 , 0 3 , 9 1 d n gr e w o p. d n u o r g y l p p u s r e w o p 7a e ot u p n ip u l l u p g n i l b a s i d d n a g n i l b a n e s l o r t n o c . n i p e l b a n e t u p t u o a k n a b . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o 3 a q : 0 a q f o 8k l ct u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c 9v d d r e w o p. n i p y l p p u s r e w o p 0 1b e ot u p n ip u l l u p g n i l b a s i d d n a g n i l b a n e s l o r t n o c . n i p e l b a n e t u p t u o b k n a b . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o 3 b q : 0 b q f o 5 1 , 4 1 , 3 1 , 2 10 b q , 1 b q , 2 b q , 3 b qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o k c o l c b k n a b 8 1c e ot u p n ip u l l u p g n i l b a s i d d n a g n i l b a n e s l o r t n o c . n i p e l b a n e t u p t u o c k n a b . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o 3 c q : 0 c q f o 3 2 , 2 2 , 1 2 , 0 20 c q , 1 c q , 2 c q , 3 c qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o k c o l c c k n a b 9 2 , 8 2 , 7 2 , 6 23 d q , 2 d q , 1 d q , 0 d qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o k c o l c d k n a b 1 3d e ot u p n ip u l l u p g n i l b a s i d d n a g n i l b a n e s l o r t n o c . n i p e l b a n e t u p t u o d k n a b . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o 3 d q : 0 d q f o : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r s t u p n is t u p t u o ] d : a [ e ok l c3 x q : 0 x q 10 w o l 11 h g i h l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v o d d v 6 2 . 1 =5 1f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u ov o d d % 5 2 . 1 =83 11 2 s t u p n i l o r t n o cs t u p t u o ] d : a [ e o3 x q : 0 x q 0z - i h 1e v i t c a
idt ? / ics ? 1-to-16, 1.2v lvcmos fanout buffer 3 ics8316ak rev. b february 29, 2008 ics8316 low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v, v ddo = 1.2v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s r e w o p 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 4 1 . 12 . 16 2 . 1v i d d t n e r r u c y l p p u s r e w o p 0 1a i o d d t n e r r u c y l p p u s t u p t u o 0 1a a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 34.8c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4b. lvcmos dc c haracteristics , t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i k l cv d d v = n i v 5 6 4 . 3 =0 5 1a d e o : a e ov d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i k l cv d d v , v 5 6 4 . 3 = n i v 0 =5 -a d e o : a e ov d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v h o e g a t l o v h g i h t u p t u ov o d d 1 e t o n ; % 5 v 2 . 1 =v o d d 7 . 0 *v v l o e g a t l o v w o l t u p t u ov o d d 1 e t o n ; % 5 v 2 . 1 =v o d d 3 . 0 *v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o d d . m a r g a i d " t i u c r i c t s e t d a o l " , n o i t c e s t n e m e r u s a e m r e t e m a r a p e e s . 2 / t able 5. ac c haracteristics , v dd = 3.3v5%, v ddo = 1.2v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 5 1z h m p t h l 1 e t o n ; h g i h o t w o l y a l e d n o i t a g a p o r p 3 . 25 4 . 36 . 4s n t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 0 8 3s p t ) b ( k s4 , 3 e t o n ; w e k s k n a b 0 7s p t ) p p ( k s5 , 3 e t o n ; w e k s t r a p - o t - t r a p 2 . 1s n t r /t f e m i t e s i r t u p t u o% 0 8 o t % 0 20 5 30 5 8s p c d oe l c y c y t u d t u p t u ot u o f z h m 0 0 17 43 5% f t a d e r u s a e m s r e t e m a r a p l l a x a m . e s i w r e h t o d e t o n s s e l n u v m o r f d e r u s a e m : 1 e t o n d d v o t t u p n i e h t f o 2 / o d d . t u p t u o e h t f o 2 / v t a d e r u s a e m . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n o d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v e m a s e h t t a s t u p t u o f o k n a b a n i h t i w w e k s s a d e n i f e d : 4 e t o n l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s e h t s a d e n i f e d : 5 e t o n v t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l o d d . 2 /
idt ? / ics ? 1-to-16, 1.2v lvcmos fanout buffer 4 ics8316ak rev. b february 29, 2008 ics8316 low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs clock outputs 20% 80% 80% 20% t r t f t period t pw t period odc = v ddo 2 x 100% t pw t pd v dd 2 v ddo 2 clk qa0:qa3, qb0:qb3, qc0:qc3, qd0:qd3 o utput r ise /f all t ime qa0:qa3, qb0:qb3, qc0:qc3, qd0:qd3 p arameter m easurement i nformation scope qx lvcmos 2.7v5% v ddo -0.6v5% v dd 0.6v5% p art - to -p art s kew gnd o utput d uty c ycle /p luse w idth /p eriod p ropagation d elay t sk(o) v ddo 2 v ddo 2 qy qx t sk(pp) v ddo 2 v ddo 2 qy qx part 1 part 2 b ank s kew ( where x denotes outputs in the same bank ) t sk(b) v ddo 2 v ddo 2 qx0:qx3 qx0:qx3 o utput s kew 3.3v c ore /1.2v o utput l oad ac t est c ircuit
idt ? / ics ? 1-to-16, 1.2v lvcmos fanout buffer 5 ics8316ak rev. b february 29, 2008 ics8316 low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs a pplication i nformation i nputs : lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utputs all unused lvcmos output can be left floating. we recommend that there is no trace attached. f igure 1. p.c.a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p at h in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 1. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadfame base pac kage, amkor technology. thermal via land pattern solder pin solder pin pad pin pad pin ground plane exposed heat slug (ground pad)
idt ? / ics ? 1-to-16, 1.2v lvcmos fanout buffer 6 ics8316ak rev. b february 29, 2008 ics8316 low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs r eliability i nformation t ransistor c ount the transistor count for ics8316 is: 416 t able 6. ja vs . a ir f low t able for 32 l ead vfqfn ja vs. 0 air flow (linear feet per minute) 0 multi-layer pcb, jedec standard test boards 34.8c/w
idt ? / ics ? 1-to-16, 1.2v lvcmos fanout buffer 7 ics8316ak rev. b february 29, 2008 ics8316 low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs t able 7. p ackage d imensions p ackage o utline and d imensions - k s uffix for 32 l ead vfqfn reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s 2 - d h h v m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 8 . 0- -0 0 . 1 1 a 0- -5 0 . 0 3 a . f e r 5 2 . 0 b 8 1 . 05 2 . 00 3 . 0 n d 8 n e 8 d c i s a b 0 0 . 5 2 d 0 . 33 . 3 e c i s a b 0 0 . 5 2 e 0 . 33 . 3 e c i s a b 0 5 . 0 l 0 3 . 00 4 . 00 5 . 0 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this draw- ing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 11 below.
idt ? / ics ? 1-to-16, 1.2v lvcmos fanout buffer 8 ics8316ak rev. b february 29, 2008 ics8316 low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs t able 8. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t k a 6 1 3 8 s c ik a 6 1 3 8 s c in f q f v d a e l 2 3y a r tc 0 7 o t c 0 t k a 6 1 3 8 s c ik a 6 1 3 8 s c in f q f v d a e l 2 3l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l k a 6 1 3 8 s c if l k a 6 1 3 8 s c in f q f v " e e r f - d a e l " d a e l 2 3y a r tc 0 7 o t c 0 t f l k a 6 1 3 8 s c if l k a 6 1 3 8 s c in f q f v " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
idt ? / ics ? 1-to-16, 1.2v lvcmos fanout buffer 9 ics8316ak rev. b february 29, 2008 ics8316 low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b 5 t 7 t 1 3 5 7 7 . t e l l u b w e k s t u p t u o d e t a d p u - n o i t c e s s e r u t a e f m o r f r e t e m a r a p w e k s t u p t u o d e g n a h c n c p r e p - e l b a t s c i t s i r e t c a r a h c c a . x a m s p 0 8 3 o t . x a m s p 0 4 1 . x a m s p 0 7 o t . x a m s p 0 6 m o r f w e k s k n a b d e g n a h c d n a . n o i t c e s h t a p e s a e l e r l a m r e h t n f q f v d e d d a . e n i l t u o e g a k c a p o t e t o n d e d d a . s t n e m e r u s a e m 2 e / 2 d d e t c e r r o c - e l b a t s n o i s n e m i d e g a k c a p 8 0 / 9 2 / 2
ics8316 low skew, 1-to-16, lvcmos/lvttl fanout buffer w/1.2v lvcmos outputs innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia integrated device technology idt (s) pte. ltd. 1 kallang sector, #07-01/06 kolam ayer industrial park singapore 349276 +65 6 744 3356 +65 6 744 1764 (fax) europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 +44 (0) 1372 378851 (fax) ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brand s, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa japan nippon idt kk sanbancho tokyu bld. 7f, 8-1 sanbancho chiyoda-ku, tokyo 102-0075 +81 3 3221 9822 +81 3 3221 9824 (fax)
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